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AnaGate UP 2.0 - Firmware Changelog

In the following you will find information about changes of actual and older firmware versions of the AnaGate UP 2.0. 

AnaGate UP 2.0 Firmware

Revision History
Revision 2.0.811.06.2015JGo
  • new FPGA.bit: clock mode 3 inverted MOSI instead of Clock line

Revision 2.0.713.04.2015JGo
  • Bugfix (temp): set minimal SPI baudrate to 330000

Revision 2.0.617.12.2014JGo
  • Bugfix: configure and set DIOs only once at startup instead of every time a connection is opened

  • Bugfix: GetGlobals set polarity to on

Revision 2.0.505.08.2013JGo
  • program FPGA just once on start-up instead of every time a connection is established (saves about 1 second per connection)

Revision 2.0.412.02.2013JGo
  • enabled compiler optimisations

  • switched from CommonLib to libAnaGate und libAnaGateExt

  • I2C: detect and process Arbitration Lost

  • SPI: added more performant asymmetric Transceive implementation

  • SPI: added Sequence command

Revision 2.0.002.02.2013JGo
  • Initial version, based on Firmware AnaGate UP 1.3.3

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